Guide
ATtiny 0/1/2-Series Pinout
The complete pin reference for Microchip’s modern ATtiny 0/1/2-series: true USART, SPI and I2C peripherals, and single-wire UPDI programming instead of classic ISP.
- AVRxt core, up to 20 MHz
- UPDI programming
- 2–32 KB flash
- 1.8V – 5.5V
Overview
The ATtiny 0-, 1- and 2-series are Microchip’s modern successors to the classic ATtiny85: a faster AVRxt core, real USART/SPI/I2C peripherals instead of a shared USI, and single-wire UPDI programming instead of the 4-wire ISP the ATtiny85 uses. This guide uses the 14-pin SOIC package (the “x04/x14/x24” members, e.g. ATtiny214/414/814) as the reference, larger parts in the family add a PORTC and extra PORTB pins.
Getting started
You’ll need a UPDI programmer, either a dedicated one, or a cheap USB-to-serial adapter wired as a “SerialUPDI” programmer (a single resistor between TX and RX does the trick).
How it compares to the ATtiny85
| Feature | ATtiny85 (classic) | ATtiny 0/1/2-series (modern) |
|---|---|---|
| CPU core | Classic AVR | AVRxt (faster, more efficient) |
| Flash | 8 KB | 2–32 KB |
| SRAM | 512 B | 128 B – 2 KB |
| ADC | 10-bit | 10- or 12-bit |
| DAC | No | Yes (some models) |
| Timers | 2 | 3+ (advanced) |
| Peripherals | USI (SPI/I2C) | True USART, SPI, I2C |
| Programming | ISP (4-wire) | UPDI (1-wire) |
| Power range | 2.7V – 5.5V | 1.8V – 5.5V |
Pin reference (14-pin SOIC)
Pin count and some peripherals vary across the family, this table and diagram use the 14-pin SOIC package shared by the ATtiny214/414/814.
| Pin | Name | Functions |
|---|---|---|
| 1 | VDD | Power supply (1.8 – 5.5V) |
| 2 | PA4 | Analog (AIN4), PTC X0/Y0, digital I/O |
| 3 | PA5 | Analog (AIN5), PTC X1/Y1, digital I/O |
| 4 | PA6 | Analog (AIN6), PTC X2/Y2, digital I/O |
| 5 | PA7 | Analog (AIN7), PTC X3/Y3, digital I/O |
| 6 | PB3 | TOSC1 (timer oscillator), digital I/O |
| 7 | PB2 | TOSC2, EVOUT1, digital I/O |
| 8 | PB1 | Analog (AIN10), PTC X4/Y4, TWI SDA (alt), USART XCK (alt), digital I/O |
| 9 | PB0 | Analog (AIN11), PTC X5/Y5, TWI SCL (alt), USART XDIR (alt), digital I/O |
| 10 | PA0 | nRESET, UPDI, analog (AIN0), digital I/O |
| 11 | PA1 | Analog (AIN1), BREAK, USART TXD (alt), SPI MOSI, TWI SDA |
| 12 | PA2 | Analog (AIN2), EVOUT0, USART RXD (alt), SPI MISO, TWI SCL |
| 13 | PA3 | EXTCLK, analog (AIN3), USART XCK, SPI SCK |
| 14 | GND | Ground |
Programming (UPDI)
A single pin handles programming here, no separate MOSI/MISO/SCK like the ATtiny85’s ISP header.
| Function | Pin | Description |
|---|---|---|
| UPDI | PA0 | Also the reset pin, single-wire programming and debugging |
| VCC | Pin 1 | Power the chip while programming |
| GND | Pin 14 | Common ground with the programmer |
Safety notes
Before you wire anything up
- PA0 doubles as UPDI and reset, avoid tying it directly to ground or a strong pull-down if you want to reprogram the chip later.
- Check your exact chip’s datasheet before assuming a pin has a DAC or a second ADC, these vary across the 0/1/2-series.
- This family runs from 1.8V to 5.5V, but not every peripheral (like the DAC) works across the full range, check the datasheet’s electrical characteristics.
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